Espressif Systems /ESP32-C3 /SYSTEM /PERIP_CLK_EN1

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Interpret as PERIP_CLK_EN1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CRYPTO_AES_CLK_EN)CRYPTO_AES_CLK_EN 0 (CRYPTO_SHA_CLK_EN)CRYPTO_SHA_CLK_EN 0 (CRYPTO_RSA_CLK_EN)CRYPTO_RSA_CLK_EN 0 (CRYPTO_DS_CLK_EN)CRYPTO_DS_CLK_EN 0 (CRYPTO_HMAC_CLK_EN)CRYPTO_HMAC_CLK_EN 0 (DMA_CLK_EN)DMA_CLK_EN 0 (SDIO_HOST_CLK_EN)SDIO_HOST_CLK_EN 0 (LCD_CAM_CLK_EN)LCD_CAM_CLK_EN 0 (UART2_CLK_EN)UART2_CLK_EN 0 (TSENS_CLK_EN)TSENS_CLK_EN

Description

peripheral clock gating register

Fields

CRYPTO_AES_CLK_EN

reg_crypto_aes_clk_en

CRYPTO_SHA_CLK_EN

reg_crypto_sha_clk_en

CRYPTO_RSA_CLK_EN

reg_crypto_rsa_clk_en

CRYPTO_DS_CLK_EN

reg_crypto_ds_clk_en

CRYPTO_HMAC_CLK_EN

reg_crypto_hmac_clk_en

DMA_CLK_EN

reg_dma_clk_en

SDIO_HOST_CLK_EN

reg_sdio_host_clk_en

LCD_CAM_CLK_EN

reg_lcd_cam_clk_en

UART2_CLK_EN

reg_uart2_clk_en

TSENS_CLK_EN

reg_tsens_clk_en

Links

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